例句與造句

1. This paper introduces the history of the gpu firstly , and then it analyses the pipeline architecture of gpu . finally , it introduces several types of program languages of gpu
   本文首先介紹了可編程圖形硬件的發(fā)展，然后分析了它的流水線結構，最后介紹了幾種最新的編程語言。
2. And it presents the method that the filter is analyze to lifting process . we use the folding and pipeline architecture to deal with this kind of novel dwt
   本論文提出一種根據jpeg2000標準將9 7濾波器分解為提升過程矩陣乘積的形式，使用流水線的思想的新型離散小波變換結構。
3. After analyzing and comparing different partition rules , md32 pipeline architecture is finally defined , which meets the required instruction function , frequency and timing spec of md32 . a complete set of creative design method for risc / dsp md32 micro - architecture is presented , such as parallel design , internal pipeline , central control , etc . thanks to the adoption of these design methodology , control path and data path are separated , circuit delay is reduced , and complex instruction operations are balanced among multiple pipeline stages
   它們將若干復雜指令操作均勻分配在幾個流水節(jié)拍內完成，實現(xiàn)了任意窗口尋址等復雜指令操作，將整個處理器的數(shù)據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統(tǒng)時鐘頻率的要求，構成了統(tǒng)一的、緊密聯(lián)系的、協(xié)調的md32系統(tǒng)結構。
4. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too
   詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
5. It's difficult to find pipeline architecture in a sentence. 用pipeline architecture造句挺難的